//------------------------------------------------------------
//  Filename: speaker_proc.v
//   
//  Author  : wlduan@gmail.com
//  Revise  : 2016-10-10 18:15
//  Description: 
//   
//  Copyright (C) 2014, YRBD, Inc. 					      
//  All Rights Reserved.                                       
//-------------------------------------------------------------
//
`timescale 1ns/1ps
 
module SPEAKER_PROC ( 
    input clk_100mhz,  
    input rst,  

    input  wire [31:0] beep_cntr,     // in 1/100 us
    input  wire [31:0] tone_divider,  // in 1/100 us ,tone
    output reg         beep  
);      
//--------------------------------------------------------
wire clk = clk_100mhz;
reg speaker;
reg [31:0] tone_cntr;
//--------------------------------------------------------
always @(posedge clk,posedge rst) begin
    if(rst)begin 
        tone_cntr <= 0;
    end 
    else if(tone_divider > 100000000) begin
        tone_cntr <= 0;
    end    
    else begin 
        tone_cntr <= (tone_cntr > tone_divider)?0:(tone_cntr + 1);
    end 
end 
//--------------------------------------------------------
always @(posedge clk,posedge rst) begin
    if(rst)begin 
        speaker <= 1'b0;  
    end 
    else if(tone_divider > 100000000) begin
        speaker <= 1'b0;
    end
    else begin
        speaker <= (tone_cntr > tone_divider)?~speaker:speaker;
    end      
end      
//--------------------------------------------------------
always @(posedge clk) beep <= (beep_cntr > 0)? speaker:1'b1;

endmodule
